The present invention relates to a semiconductor package, a stacked wafer level package having the same and a method for fabricating the stacked wafer level package.
In recent, there have been developed a semiconductor chip adapted to store massive data and process the stored data in short time, and a semiconductor package having the semiconductor chip.
A semiconductor package is fabricated through a semiconductor chip fabrication process for fabricating a semiconductor chip by integrating devices such as a transistor, a resistor, a capacitor, etc. on a wafer and a packaging process for singulating the semiconductor chip from the wafer, connecting electrically it with an external circuit board and packaging the semiconductor chip with weak brittleness to protect it from external impact and/or vibration.
Recently, with development in packaging process technologies, there has been developed a wafer level package having a size no other than 100% to 105% of a semiconductor chip size and a stacked semiconductor package stacked with a plurality of semiconductor chips.
The wafer level package has advantages of less volume, less weight and high speed data processing.
In general, a wafer level package has a redistribution pattern connected with a bonding pad of a semiconductor chip and includes an insulation layer having an opening for exposing some portion of the redistribution pattern. To the redistribution pattern exposed by the opening of the insulation layer, a solder ball is attached.
Recently, in order to enhance data storage capacity and data processing speed of the wafer level package, studies for realizing “a stacked wafer level package” have been made. However, there has a problem that it is impossible to stack a plurality of wafer level packages due to the redistribution pattern disposed on a surface of the wafer level package and the solder ball attached to the redistribution pattern.